This invention relates to fine-line lithography and, more specifically, to a technique for improving the performance of a charged-particle-beam lithographic system designed to fabricate large-scale-integrated (LSI) or very-large-scale-integrated (VLSI) circuits.
It is known that electron- and ion-beam exposure systems constitute attractive lithographic tools for fabricating LSI and VLSI circuits. But charge deposited by an electron or ion beam onto a workpiece during alignment or writing operations in such a lithographic system tends to accumulate on the workpiece. In turn, this produces charged regions characterized by spatially variable and time-dependent electric fields. If large enough, these fields can spuriously deflect the beam incident on the workpiece and thereby cause registration and pattern placement errors in the fabrication process. Such errors can seriously degrade the performance of the lithographic system and in practice make the attainment of high-resolution circuits with such a system costly if not impossible.
Accordingly, continuing efforts have been made by workers in the LSI and VLSI circuit art directed at trying to alleviate the aforenoted charge accumulation problem in lithographic systems. It was recognized that such efforts, if successful, could significantly improve the capability of charged-particle-beam lithographic systems to accurately delineate high-resolution patterns in an integrated circuit fabrication sequence.